The present invention relates to a packet processing circuit and, more particularly, to a technique for reducing the power consumption of a packet processing circuit.
In the Internet society, as broadband networks and leased circuit type IP connection are spreading, increases in power of apparatuses and full-time energization are causing problems of power cost and global warming.
Generally, however, in the lines of an access system, the time in which packets are actually transmitted is very short. In most time, no packets are transmitted. Even in this state, a general packet processing circuit always receives clocks and consumes power independently of the presence/absence of a packet.
To reduce the power consumption in a conventional packet processing circuit, a technique has been proposed, in which a gate signal is applied, for each word of data, to clocks of a flip-flop, thereby validating the clocks only when the data changes (e.g., Japanese Patent Laid-Open No. 2001-177382 (pp. 7-10, FIG. 1)).
However, in this technique, the gating unit is small, and the number of control circuits increases.